Electrostatic discharge (ESD) events can cause damage to elements of circuitry due to excessively high voltages or currents. For example, the propagation of an ESD event through a circuit may cause a transistor to greatly exceed its voltage or current capacity, suffer physical damage, and subsequently fail. The potential for failure increases as circuitry becomes smaller and as operating voltage levels are reduced. ESD events may occur due to a relatively short period of relatively high voltage or current imposed on a device. For example, ESD events are sometimes caused by contact with the human body, by machinery such as manufacturing or test equipment, or in electrically active environments, as may be incurred in many consumer applications. A variety of ESD events can occur in electronic devices, including discharge between the pads of an integrated circuit, discharge between voltage supply terminals, and discharge between pads and voltage supply terminals. Various kinds of ESD protection circuitry are used in the art to protect ICs from damage due to the occurrence of ESD events during manufacture, testing, and operation. In general, ESD protection circuitry is designed to protect the input/output circuitry and internal circuitry of an integrated circuit from excessively large and sudden discharges of electrostatic energy.
Integrated circuits must be protected against electrostatic discharges in order to prevent permanent damage that can impair or eliminate desired functionality. ESD damage normally occurs in the MOSFET devices or interconnecting layers used to couple MOSFETs together to form a circuit. Each pin in an integrated circuit must be coupled to an appropriate ESD protection circuit such that the ESD discharge current is shunted away from the internal portions of the chip that are the most sensitive to damage. As such, ESD discharge paths must be provided between every pair of pins in an IC for both positive and negative polarities.
The objective for ESD protection in general is to provide a shunting path for each potentially damaging ESD path. A shunting path is required to the top rail for ESD currents produced by ESD potentials applied to the protected node which are significantly more positive than anywhere else on the IC. Similarly, a shunting path is desirable for ESD currents that are produced by ESD potentials that are significantly more negative than elsewhere on the IC. A rail clamp is desirable to provide a coupling between the top and bottom rails for those ESD paths that require such a coupling in order to complete the discharge loop. In general, the goal is to keep the maximum voltage in the discharge loop within acceptable limits.
Just as ESD pulses can be applied between the I/O pads and the supply rails, ESD discharges can occur between the power supply rails. For example, for top rail to bottom rail stress, ESD current typically flows through a rail clamp from the top rail to the bottom rail. For bottom rail to top rail stress, ESD current flows from the bottom rail to the top rail. A rail clamp circuit is typically a fundamental component in providing a discharge path for ESD polarities which cause the first current electrode of the rail clamp to be more positive than its second current electrode. For polarities which cause the second current electrode of the rail clamp to be more positive than the first, a power bus diode normally provides an ESD dissipation path. This power bus diode often exists by default in an integrated circuit and is normally reversed biased during normal operation.
ESD discharges are brief transient events that are usually less than one microsecond in duration. Furthermore, the rise times associated with these brief pulses are usually less than approximately twenty nanoseconds. When ESD pulses are applied to the I/O pads of a chip, they produce similar brief, quickly rising potentials on the power supply rails due to the presence of ESD protection. The rail clamp circuit must be able to detect these fast transients and begin conducting so as to shunt the resulting ESD current. However, the rail clamp must not respond to the much slower rise times (greater than 1 millisecond) which are present on the power supply rails during normal power-up events in usual chip operation. If the ESD rail clamp were to trigger and conduct during normal power-up events, the desired operation of the IC could be compromised. Furthermore, in addition to triggering when needed for ESD protection, the rail clamp circuits must stay in a highly conductive state for the entire duration of the ESD pulse so that all of the ESD energy is safely discharged. If the rail clamp circuit were to shut-off prematurely, damaging potentials would build up quickly between the power rails and cause device failure.
It is known to place a rail clamp in the bottom rail pads in the chip that are responsible for supplying power connections for the IC. The rail clamp may also be placed in the top rail pads. These placements are sometimes made so that numerous I/O cells share ESD rail clamps, ensuring more robust ESD protection and reduced die area. Alternatively, the size of an individual rail clamp can be reduced, in order to conserve die area, if more than one clamp can be relied upon to conduct ESD current. In general, the sum total of parasitic power and ground rail resistances around the ESD discharge loop sets the limit on how far apart ESD rail clamps may be spaced in order to achieve a given level of ESD protection. One of the overall design goals is to keep the maximum voltage that occurs at the bond pad during an ESD discharge within acceptable limits so that damage does not occur in sensitive circuit elements.
In an effort to mitigate the effects of parasitic bus resistance, ESD rail clamps may be distributed locally in the I/O cells themselves. In this manner, several ESD rail clamps participate in the ESD event to provide robust protection. In this way, the effects of power and ground rail resistances may also be reduced in comparison with placing fewer, larger clamps in more centralized locations. In general, one skilled in the art is required to balance the tradeoff among ESD protection, resistance, and chip area.
Due to these and other problems, a need exists for circuits and methods that provide microelectronic circuits with reduced area, low leakage, and with the ability to withstand ESD events without adversely impacting the performance of the functional circuit path during normal operation.